The integration density of semiconductor devices has quadrupled over a short period of time. This feat has been accomplished by miniaturization of the size of the device, according to demanding ground rules for fabrication. Common features on or within a typical device, such as electrical studs, isolation trenches, and wiring patterns, have had to be positioned unusually close to each other.
The extreme proximity of conductive elements may result in serious problems if the elements are designed to be insulated from one another. Inadvertent contact can lead to electrical shorts and failure of the semiconductor device. In a multi-level device in which each level contains various conductive elements, the problem can be especially difficult. For example, in a given device, some of the conductive elements on a lower level are designed to contact conductive elements on an adjacent upper level, while other lower level conductive elements perform different functions and must remain isolated from upper level elements which happen to be situated immediately above them. However, in preparing the device, conventional patterning and etching steps (e.g., directional reactive ion etching (RIE)) may not discriminate between elements which are designed to contact each other, and those requiring separation by way of an intervening insulating layer. Of course, various masking steps could be employed to prevent the unwanted exposure of one particular conductive element to another. However, increasing the number of masking and patterning steps often adds complexity to the overall device fabrication process. This in turn can decrease manufacturing productivity and increase overall costs.
One example of a semiconductor structure susceptible to this problem is a dynamic random access memory (DRAM) device. High density DRAM's often utilize stacked capacitor (STC) cells, which provide a great deal of storage capability. An illustration of DRAM devices utilizing some form of STC technology is found in U.S. Pat. Nos. 5,196,910 and 5,140,389, as well as in an article by Y. Kawamoto et al. in the 1990 Symposium on VLSI Technology, pages 13-14, entitled "A 1.28 um.sup.2 Bit-Line Shielded Memory Cell Technology for 64 Mb DRAMs". The general design and function of STC cells utilized in random access memory is known in the art. These cells represent key elements in the design of high-speed, low-power DRAM's of the 64 megabit class.
The Kawamoto article mentioned above describes a "bit-line shielded" STC cell, in which the storage capacitor--a cylindrical node or "chimney"--is formed over a bit-line. The cell also contains the other necessary functional terminal for memory, i.e., a word line. The article also includes the description of a method for fabricating the storage cell.
A version of a typical STC cell is provided in FIG. 1. Many of the features in this figure are similar to those in the device of the Kawamoto article, although this version of an STC cell utilizes a bit-line stud and a capacitor stud. The use of studs can result in a denser, more integrated cell. Such a cell often tends to function with lower bit-line and word line capacitance, which is usually very desirable. Also, the overall process involved in forming a stud-structure type of cell utilizes intermediate (i.e., as-formed) surfaces which are more "planar". In contrast, the type of cell described in Kawamoto involves intermediate surfaces which are less planar, i.e., more conformal. Greater planarity allows for easier focusing of printing tools during photolithographic steps.
Most of the techniques for forming such a cell will be described further on in the specification, with reference to FIGS. 3-6, which are based on the present invention. With reference to FIG. 1, this type of cell is generally disposed on silicon substrate 10, in which shallow trench oxide (STI) regions 12A and 12B are formed. Impurity diffusion regions 14A and, 14B abut the STI regions.
An etch stop layer 16 is usually formed over the STI regions, and then insulating region 18 is applied over layer 16. Word line 20 (formed as described below) is surrounded by insulating cap layer 26, and cap layer spacers 27A and 27B. Bit-line stud 22 and capacitor stud 24 are situated within region 18, and are separated by oxide layer 28 and a portion 30 of insulating region 18. Both of the studs are made of a conductive material. Stud differentiation layer 34 is deposited or formed on a portion of the exposed surfaces of insulating region 18. Bit-line 36 can be formed as described below, and contacts a portion of the upper surface of bit-line stud 22. The bit-line is usually covered by an insulating bit-line cap layer 38.
Storage capacitor nodes 40 and 42 constitute the main storage elements in the STC. They can be prepared by various techniques, such as the one described in the Kawamoto article. The nodes themselves are usually formed of a material like polysilicon, surrounded by a node dielectric layer 48. A conductive "plate" or layer 50 covers each of the nodes.
In a highly integrated device such as this one, conductive elements may be very close to each other, but perform very different functions, and can in fact be independently connected to very different parts of the same device, or to other devices within an integrated circuit. Thus, despite their proximity, electrical contact between two elements has to be prevented sometimes to, in turn, prevent shorting and failure of the device.
As a specific example, some types of STC cells like that of FIG. 1 require contact between storage node 42 and capacitor stud 24 for proper operation. At the same time, however, these types of cells require that storage node 40 be separated, i.e., electrically isolated, from bit-line stud 22. (Node 40 may be electrically connected to an entirely different feature in the cell, or to a different device).
Keeping nearby conductors electrically isolated from each other in a highly integrated STC cell is a very difficult task because of the steps required to fabricate such a cell. In the example of FIG. 1, word line 20, cap layer 26, and studs 22 and 24 are each formed within insulating region 18 by separate, conventional steps. The studs are substantially coplanar. The required openings for all of these features are usually prepared by applying a suitable photoresist layer (not shown), and then patterning the photoresist to define the dimensions of the opening.
The defined area is directionally etched using, for example, reactive ion etching (RIE) techniques. The same types of procedures are used to form bit-line 36. The bit-line 36 is isolated from the capacitor stud 24 by the stud-differentiation layer 34, which initially was a continuous layer over insulating region 18. Bit-line 36 is isolated from subsequently-formed storage capacitor nodes 40 and 42 by spacers 37A, 37B, and by cap oxide layer 38. The storage nodes are usually formed simultaneously, via a technique such as that set forth in the Kawamoto article. As in the case of the studs, formation of the nodes of a desired size, and at a desired location, usually requires precise patterning of an applied resist in the appropriate locations, followed by etching the defined pattern.
However, the steps involved in node formation can lead to undesirable overlap between node 40 and bit-line stud 22. When stud differentiation layer 34 is first etched to allow bit-line 36 to contact bit-line stud 22, but not capacitor stud 24, the alignment may be less than exact. This results in a portion of the upper surface of stud 22 being left exposed, which in turn results in the subsequent, undesirable contact between node 40 and bit-line stud 22 (see area 32). As mentioned above, this contact may, at a minimum, cause an electrical short.
Elimination of the overlap problem is generally not possible when using current photolithographic imaging techniques to define a multitude of closely-spaced features, since these techniques require a certain minimum tolerance in the alignment of a given mask to a pattern on a substrate. In fact, the extreme emphasis on high density integration has made the overlap problem more severe.
FIG. 2 is a simplified, graphical depiction of potential, undesirable overlap between various regions on the planar surface of an STC cell being prepared (and within the cell itself), as various, sequential stages of photolithographic imaging are carried out. The figure is a plan view, as taken from the top of the structure, and includes the relative positions of capacitor stud 52, bit-line stud 53, first bit-line 54, second bit-line 55, word line 56, first capacitor node 57, and second capacitor node 58. In brief, the inability to ensure perfect alignment during imaging results in unwanted overlap between areas being defined and then etched. An illustrative area of this overlap is designated as region 59.
One technique for dealing with overlap and the undesirable consequences noted above involves the use of an additional mask specifically applied and patterned on the top surface of bit-line stud 22 (FIG. 1), prior to formation of the capacitor nodes. As noted above, however, the use of additional masks usually adds complexity and cost to the fabrication process. In fact, the use of masks for this purpose might actually become impossible as the dimensions of semiconductor structures are dramatically reduced.
It should thus be apparent that a need exists for a method of efficiently isolating conductors which happen to be situated very closely to each other, and which are formed by standard patterning and etching techniques.
The method should be applicable to very highly integrated, multi-level devices, such as stacked capacitors, without decreasing the density of the device, or exceeding the boundaries of lithographic capabilities.
Moreover, devices prepared by such a method should retain their performance capabilities. In the case of an STC cell, for example, a large storage capacitance should be maintained.